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1 document # sram114 rev b revised august 2006 features full cmos, 6t cell high speed (equal access and cycle times) ? 10/12/15/20/25 ns (commercial) ? 12/15/20/25/35 ns (industrial) ? 15/20/25/35/45 ns (military) low power operation (commercial/military) output enable and dual chip enable functions 5v 10% power supply data retention with 2.0v supply, 10 a typical current (p4c1981l/1982l military) separate inputs and outputs ? p4c1981/l input data at outputs during write ? p4c1982/l outputs in high z during write fully ttl compatible inputs and outputs standard pinout (jedec approved) ? 28-pin 300 mil dip, soj ? 28-pin 350 x 550 mil lcc ? 28-pin cerpack functional block diagram pin configurations the p4c1981/l and p4c1982/l are 65,536-bit (16kx4) ultra high-speed static rams similar to the p4c198, but with separate data i/o pins. the p4c1981/l feature a transparent write operation when oe is low; the outputs of the p4c1982/l are in high impedance during the write cycle. all devices have low power standby modes. the rams operate from a single 5v 10% tolerance power supply. with battery backup, data integrity is maintained for supply voltages down to 2.0v. current drain is typically 10 a from 2.0v supply. description access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. cmos is used to reduce power consumption. for the p4c1982l and p4c1981l, power is only 5.5 mw standby with cmos input levels. the p4c1981/l and p4c1982/l are available in 28-pin 300 mil dip and soj, 28-pin 350x550 mil lcc and a 28-pin cerpack package providing excellent board level den- sities. dip (p5, c5, d5-2), soj (j5) cerpack (f4) similar lcc (l5) p4c1981/p4c1981l, p4c1982/p4c1982l ultra high speed 16k x 4 cmos static rams p4c1981/ 1982
p4c1981/1981l, p4c1982/1982l page 2 of 13 document # sram114 rev b ce 1 , ce 2 v hc, mil. v cc = max., ind./com?l. f = 0, outputs open v in v lc or v in v hc maximum ratings (1) symbol parameter value unit v cc power supply pin with ?0.5 to +7 v respect to gnd terminal voltage with ?0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ?55 to +125 c symbol parameter value unit t bias temperature under ?55 to +125 c bias t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma recommended operating temperature and supply voltage i sb standby power supply current (ttl input levels) ce 1 , ce 2 v ih , mil. v cc = max., ind./com?l. f = max., outputs open ___ ___ 40 35 ___ ___ ___ ___ 20 15 40 n/a 1.0 n/a ma ma ___ ___ standby power supply current (cmos input levels) symbol c in c out parameter input capacitance output capacitance conditions v in = 0v v out = 0v 5 7 unit pf pf capacitances (4) v cc = 5.0v, t a = 25c, f = 1.0mhz n/a = not applicable symbol dc electrical characteristics over recommended operating temperature and supply voltage (2) v ih v il v hc v lc v cd v ol v oh i li i lo parameter input high voltage input low voltage cmos input high voltage cmos input low voltage input clamp diode voltage output low voltage (ttl load) output high voltage (ttl load) input leakage current output leakage current test conditions v cc = min., i in = ?18 ma i ol = +8 ma, v cc = min. i oh = ?4 ma, v cc = min. v cc = max. mil. v in = gnd to v cc ind./com?l. p4c1981 / 1982 min 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?10 ?5 ?10 ?5 max v cc +0.5 0.8 v cc +0.5 0.2 ?1.2 0.4 +10 +5 +10 +5 p4c1981l / 82l min max 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?5 n/a ?5 n/a v cc +0.5 0.8 v cc +0.5 0.2 0.4 ?1.2 +5 n/a +5 n/a unit v v v v v v v a a typ. industrial commercial grade (2) ambient temperature gnd v cc ?40c to +85c 0c to +70c 0v 0v 5.0v 10% 5.0v 10% 0v 5.0v 10% ?55c to +125c military i sb1 v cc = max., mil. ce 1 , ce 2 = v ih ind./com?l. v out = gnd to v cc
p4c1981/1981l, p4c1982/1982l page 3 of 13 document # sram114 rev b data retention characteristics (p4c1981l/p4c1982l military temperature only) typ.* max symbol parameter test condition min v cc =v cc = unit 2.0v 3.0v 2.0v 3.0v v dr v cc for data retention 2.0 v i ccdr data retention current 10 15 600 900 a t cdr chip deselect to ce 1 or ce 2 v cc ? 0.2v, 0 ns data retention time v in v cc ? 0.2v or t r ? operation recovery time t rc ns * t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested. notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum ratingconditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. *v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce 1 = v il , ce 2 = v il , oe = v ih i cc symbol parameter temperature range dynamic operating current* commercial industrial military ?10 n/a ?12 ?15 ?20 ?25 ?35 ?45 unit n/a ma ma ma power dissipation characteristics vs. speed n/a 150 155 160 170 180 n/a 170 160 155 150 145 180 170 160 155 150 n/a n/a v in 0.2v data retention waveform
p4c1981/1981l, p4c1982/1982l page 4 of 13 document # sram114 rev b sym. parameter unit -10 -12 -15 -20 -25 -35 -45 min max min max min max min max min max min max min max t rc read cycle time 10 12 15 20 25 35 45 ns t aa address access 10 12 15 20 25 35 45 ns time t ac chip enable 10 12 15 20 25 35 45 ns access time t oh output hold from 2 2 2222 2ns address change t lz chip enable to 2 2 2222 2ns output in low z t hz chip disable to 6 7 8 10 10 15 15 ns output in high z t oe output enable 6 7 8 12 15 21 27 ns low to data valid t olz output enable to 2 2 2222 2ns output in low z t ohz output disable to 6 7 9 9 10 14 15 ns output in high z t pu chip enable to 0 0 0000 0ns power up time t pd chip disable to 10 12 15 20 25 25 30 ns power down time ac characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) read cycle no.1 ( oe oe oe oe oe controlled) (5) notes: 5. we is high for read cycle. 6. ce 1 , ce 2 and oe are low for read cycle. 7. oe is low for the cycle. 8. address must be valid prior to or coincident with, ce 1 , and ce 2 transition low. 9. transition is measured 200mv from steady state voltage prior to change, with loading as specified in figure 1. 10. read cycle time is measured from the last valid address to the first transitioning address.
p4c1981/1981l, p4c1982/1982l page 5 of 13 document # sram114 rev b note: 11. transitions caused by a chip enable control have similar delays irrespective of whether ce 1 or ce 2 causes them. read cycle no. 3 ( ce ce ce ce ce 1 , ce ce ce ce ce 2 controlled) (5,7,8) read cycle no. 2 (address controlled) (5,6)
p4c1981/1981l, p4c1982/1982l page 6 of 13 document # sram114 rev b ac characteristics?write cycle (v cc = 5v 10%, all temperature ranges) (2) parameter symbol ?10 ?12 ?15 ?20 ?25 ?35 ?45 min max max max max max max max min min min min min min t wc t cw t aw t as write cycle time chip enable time to end of write address valid to end of write address set-up time t wz t dh t dw t ah t wp write pulse width address hold time from end of write data valid to end of write data hold time write enable to output in high z t ow output active from end of write 10 7 7 0 8 0 5 0 2 5 12 8 8 0 9 0 6 0 2 6 13 10 10 0 10 0 7 0 2 7 15 15 15 0 15 0 10 0 2 8 20 20 20 0 20 0 13 0 2 10 30 30 25 0 25 0 15 0 2 10 40 35 35 0 35 0 20 0 2 15 unit ns ns ns ns ns ns ns ns ns ns t awe t adv write enable to data-out valid (p4c1981) data-in valid to data-out valid (p4c1981) ns ns 10 10 12 12 13 13 18 18 20 30 35 35 30 20 write cycle no. 1 (with oe oe oe oe oe high)
p4c1981/1981l, p4c1982/1982l page 7 of 13 document # sram114 rev b write cycle no. 2 ( we we we we we controlled) (13,14) 1520 08 write cycle no. 3 ( ce ce ce ce ce 1 , ce ce ce ce ce 2 controlled) (11,12) notes: 12. ce ( ce 1 , ce 2 ) and we must be low for write cycle. 13. oe is low for write cycle. 14. if ce 1 or ce 2 goes high simultaneously with we high, the output remains in a high impedance state. 15. write cycle time is measured from the last valid address to the first transitioning address.
p4c1981/1981l, p4c1982/1982l page 8 of 13 document # sram114 rev b truth table p4c1981/l (p4c1982/l) ce ce ce ce ce 1 h x l l l l ce ce ce ce ce 2 x h l l l l we we we we we x x h h l l oe oe oe oe oe x x h l h l mode standby standby output inhibit read write write output high z high z high z d out high z d in (high z) input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 ac test conditions * including scope and test fixture. note: because of the ultra-high speed of the p4c1981/l and p4c1982/l, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high figure 1. output load figure 2. thevenin equivalent frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.73v (thevenin voltage) at the comparator input, and a 116 ? resistor must be used in series with d out to match 166 ? (thevenin resistance).
p4c1981/1981l, p4c1982/1982l page 9 of 13 document # sram114 rev b selection guide the p4c1981 and p4c1982 are available in the following temperature, speed and package options. * military temperature range with mil-std-883, class b processing. n/a = not available ordering information 10 12 15 20 25 35 45 plastic dip -10pc -12pc -15pc -20pc -25pc n/a n/a plastic soj -10jc -12jc -15jc -20jc -25jc n/a n/a industrial plastic dip n/a -12pi -15pi -20pi -25pi -35pi n/a plastic soj n/a -12ji -15ji -20ji -25ji -35ji n/a side brazed dip n/a n/a -15cm -20cm -25cm -35cm -45cm cerdip n/a n/a -15dm -20dm -25dm -35dm -45dm cerpack n/a n/a -15fm -20fm -25fm -35fm -45fm lcc n/a n/a -15lm -20lm -25lm -35lm -45lm side brazed dip n/a n/a -15cmb -20cmb -25cmb -35cmb -45cmb cerdip n/a n/a -15dmb -20dmb -25dmb -35dmb -45dmb cerpack n/a n/a -15fmb -20fmb -25fmb -35fmb -45fmb lcc n/a n/a -15lmb -20lmb -25lmb -35lmb -45lmb speed (ns) military temperature military processed* temperature range package commercial
p4c1981/1981l, p4c1982/1982l page 10 of 13 document # sram114 rev b pkg # # pins symbol min max a-0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d-1.485 e 0.240 0.310 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - c5 28 (300 mil) 0.300 bsc 0.100 bsc pkg # # pins symbol min max a-0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d-1.485 e 0.240 0.310 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - 0 15 d5-2 28 (300 mil) 0.300 bsc 0.100 bsc side brazed dual in-line package cerdip dual in-line package
p4c1981/1981l, p4c1982/1982l page 11 of 13 document # sram114 rev b pkg # # pins symbol min max a 0.060 0.090 b 0.015 0.022 c 0.004 0.009 d - 0.730 e 0.330 0.380 e k 0.005 0.018 l 0.250 0.370 q 0.026 0.045 s - 0.085 s1 0.005 - f4 28 0.050 bsc pkg # # pins symbol min max a 0.120 0.148 a1 0.078 - b 0.014 0.020 c 0.007 0.011 d 0.700 0.730 e e e1 0.292 0.300 e2 q0.025- j5 28 (300 mil) 0.050 bsc 0.267 bsc 0.335 bsc cerpack ceramic flat package soj small outline ic package
p4c1981/1981l, p4c1982/1982l page 12 of 13 document # sram114 rev b pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.342 0.358 d1 d2 d3 - 0.358 e 0.540 0.560 e1 e2 e3 - 0.558 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne 0.020 ref 5 9 0.400 bsc 0.200 bsc 0.050 bsc 0.040 ref l5 28 0.200 bsc 0.100 bsc pkg # # pins symbol min max a-0.210 a1 - b 0.014 0.023 b2 0.045 0.070 c 0.008 0.014 d 1.345 1.400 e1 0.270 0.300 e 0.300 0.380 e eb - 0.430 l 0.115 0.150 0 15 0.100 bsc p5 28 (300 mil) rectangular leadless chip carrier plastic dual in-line package
p4c1981/1981l, p4c1982/1982l page 13 of 13 document # sram114 rev b revisions document number : sram114 document title : p4c1981 / p4c198l, p4c1982 / p4c1982l ultra high speed 16k x 4 static cmos rams rev. issue date orig. of change description of change or 1997 dab new data sheet a oct-05 jdb change logo to pyramid b aug-06 jdb updated soj package information

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